All students of CS501 are directed to participate in the GDB that will be opened from February 17, 2014 to February 18, 2014.
GDB answer via email or through MDB will not be accepted.
Note: Your answer should not be greater than 200 words.
Topic:
Do data hazards completely eradicated from our latest pipelined processors. If so, what are the modern techniques to get rid of these hazards?
Justify your answer with appropriate reason
There are several main solutions and algorithms used to resolve data hazards:
insert a pipeline bubble whenever a read after write (RAW) dependency is encountered, guaranteed to increase latency, or
utilize out-of-order execution to potentially prevent the need for pipeline bubbles
utilize register forwarding to use data from later stages in the pipeline
In the case of out-of-order execution, the algorithm used can be:
score boarding, in which case a pipeline bubble will only be needed when there is no functional unit available
the Tomasulo algorithm, which utilizes register renaming allowing the continual issuing of instructionS.
A hazard is created whenever there is a dependence between instructions, and they are close enough that the overlap caused by pipelining would change the order of access to an operand. Our example hazards have all been with register operands, but it is also possible to create a dependence by writing and reading the same memory location. In DLX pipeline, however, memory references are always kept in order, preventing this type of hazard from arising.
All the data hazards discussed here involve registers within the CPU. By convention, the hazards are named by the ordering in the program that must be preserved by the pipeline.
RAW (read after write)
WAW (write after write)
WAR (write after reAd)